Thin film transistors (TFTs) are gaining acceptance in the semiconductor industry. In fact, TFT devices have already found application in both flat panel displays and in static memory devices. In the case of static memory devices, complementary metal oxide semiconductor (CMOS) and bipolar metal oxide semiconductor (BiCMOS) static random access memories (SRAMs) have in the past predominantly used polysilicon resistor load devices. The semiconductor industry's continual drive toward higher density SRAMs, however, makes the replacement of these traditional polysilicon resistor load devices with TFT devices very desirable. Both SRAMs and flat panel displays require well-behaved TFT devices that exhibit low leakage currents and high on/off current ratios and low defectivity. In addition, high density SRAMs require TFT devices that are compatible with small memory cell sizes.
Several different TFT devices such as, vertical, over-gated, and undergated have been proposed in the past. However, the utilization of undergated TFTs in high density SRAMs has been limited. In an SRAM cell the drain electrode of the TFT must be electrically coupled to the control electrode of the latch transistor. However, electrically coupling the drain electrode of an under-gated TFT to the control electrode of the latch transistor requires an additional level of metallization. The area required for laying out the additional level of metallization is substantial and thus limits the memory cell size that can be achieved with under-gated TFTs. Accordingly, a need exists for a TFT device, which is compatible with high device density requirements.